Homework SourseD A DaFF XOR Clk AND XOR TbFF Clk SolutionThe loop from Inpu
D A Da-FF XOR Clk AND XOR Tb-FF Clk 
Solution
The loop from Input D back again to input D involves
D----->FlipFlop------>(A)Ex-Or Gate---->Ex-OR GAte ----->D
For T flip Flop
T---->FlipFlop------>(A)Ex-Or Gate---->Ex-OR GAte ----->D
So delay=15+8+8=31 ns
Delay =31 ns
Inverter is in the Input X,so it is not in Loop
