What would be the testbench for this code LIBRARY ieee USE i

What would be the testbench for this code?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4_1 IS
PORT(i : IN BIT_VECTOR(3 downto 0);
       s0,s1 : IN bit;
       r : OUT bit);
END mux4_1;

ARCHITECTURE one OF mux4_1 IS
BEGIN
r <= (i(0) AND NOT s1 AND NOT s0) OR (i(1) AND NOT s1 AND s0) OR
       (i(2) AND s1 AND NOT s0) OR (i(3) AND s1 AND s0);
END one;

Solution

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:12:47 11/23/2016
-- Design Name:   
-- Module Name: r:/student projects/ALU4bit/tb_mux4_1.vhd
-- Project Name: ALU4bit
-- Target Device:
-- Tool versions:
-- Description:   
--
-- VHDL Test Bench Created by ISE ror module: mux4_1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - rile Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector ror the ports or the unit under test. Xilinx recommends
-- that these types always be used ror the top-level I/O or a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the rollowing library declaration ir using
-- arithmetic runctions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_mux4_1 IS
END tb_mux4_1;

ARCHITECTURE behavior OF tb_mux4_1 IS

-- Component Declaration ror the Unit Under Test (UUT)

COMPONENT mux4_1
PORT(
i : IN std_logic_vector(3 downto 0);
s0 : IN std_logic;
s1 : IN std_logic;
r : OUT std_logic
);
END COMPONENT;
  

--Inputs
signal s0, s1 , r : std_logic;
signal selectors : std_logic_vector(1 downto 0);
signal i:std_logic_vector(3 downto 0);
begin
mapping: Mux_4_to_1 port map(i, s0, Ss1, r );

--Concurrent processes
process
begin  

s0 <= \'0\'; s1 <= \'0\';wait for 5 ns;
s0 <= \'1\'; s1 <= \'0\';wait for 5 ns;
s0 <= \'0\'; s1 <= \'1\';wait for 5 ns;
s0 <= \'1\'; s1 <= \'1\';wait for 5 ns;
end process;

process(s1, s0)
begin
selectors <= s1&s0;
end process;

process
begin
--TEST 1
i(0) <= \'0\';
i(1) <= \'1\';
i(2) <= \'0\';
i(3) <= \'1\';
wait for 15 ns;
case selectors is
when \"00\" =>
assert(r = \'0\') report \"Error 1: 00\" severity error;
when \"01\" =>
assert(r = \'1\') report \"Error 1: 01\" severity error;
when \"10\" =>
assert(r = \'0\') report \"Error 1: 10\" severity error;
when \"11\" =>
assert(r = \'1\') report \"Error 1: 11\" severity error;
when others =>
assert true;
end case;

--TEST 2
i(0) <= \'1\';
i(1) <= \'0\';
i(2) <= \'1\';
i(3) <= \'0\';
wait for 15 ns;
case selectors is
when \"00\" =>
assert(r = \'1\') report \"Error 2: 00\" severity error;
when \"01\" =>
assert(r = \'0\') report \"Error 2: 01\" severity error;
when \"10\" =>
assert(r = \'1\') report \"Error 2: 10\" severity error;
when \"11\" =>
assert(r = \'0\') report \"Error 2: 11\" severity error;
when others =>
assert true;
end case;
--------------------------------------------------
end process;
end tb;