Homework SourseFor the figure specify the memory if PROM0 PROM1 RAM and EEP
Solution
First it should be clear the operation of the decoder, for this case has denied outputs, so when any output is set to 1 theoretically by that denier will be 0 and therefore the other outputs will go to 1. Ok so now to this case PROM-0, PROM-1 and RAM are connected to the address bus from A0 to A12 having a width of 13bits this address has the function to choose the memory cell where the information will be collected, now for the memory this EEPROM has a smaller address bus only 11 bits from A0 to A10 this because it has less memory cells, also is connected to line 3 decoder clock enablement. While the PROM-0, PROM and RAM-1 are connected to the lines 0.1 and 2 decoder that enable clock for each.
If we wanted that memories were connected as 4,5,6 and 7 is specified, alter the design remember that each system design is different and depends on what you want to implement, in this case when A, B and C are 0 one clock is sent to the PROM-0 memory, when a is 1, C and B equal to 0 the flank to the PROM-1 memory will be sent and so on with the others, now if this is changed and connected to the lines 4,5,6 and 7 exchange and would be pulling out all the information of the memories later and also addressing may also change.
In conclusion these memories will be connected to the first decoder output lines because if connected on lines 4,5,6 and 7 respectively can cause problems with addresses and information that would shed these memory, obviously this will depend design and what you want to implement, remember the operation of the decoder and especially this that has the negated outputs, for example in this case when a, B and C are 0 line 0 of the output will be 0 too, and 1 other will depend on the coding both the entrance and designer where you want to place the lines.
