Briefly discuss pipelined instruction execution in computer

Briefly discuss pipelined instruction execution in computer. If a CPU has an N-stage instruction pipeline, what is its performance improvement ratio compared with its non-pipelined instruction design? What is pipeline registers for? Briefly discuss PICI 18F46K22^s 2-stage pipeline instruction execution. Why the PIC18F MCU can deliver 10 MIPS peak performance when clocked at 40 MHz?

Solution

a. Pipelined Instruction Execution in computer primarilly consistes of three stages: Fetch, Decode and Execute. When one instruction is being executed, the second one is being decoded and third one is being fecthed in synchronization with the system clock

c. The pipeline registers are used to hold and store the instructions to be executed, decode and fetched.

d. Instruction Fetching in one machine cycle and Instruction decoding and execution in one machine cyscle.

e. Microchip PIC18 microcontrollers have one instruction every machine cycle and a machine cycle is 4 clock cycles. Therefore, 10 MIPS at 40 KHz.