How to code a truly random number generator in vhdl Quartus

Solution

The heart of the VHDL code for random number generation: process variable s1:positive ; variable s2 :positive ; variable r1 : integer; variable r2 : real ; begin if = \'1\' then uniform (s1,s2,r2); re1 := integer (r2 * real(2**13 -1)); num_bin <= std_logic_vector ( to_int (re1,13)); end if; end process;