Create a Verilog module named if2to4 that represents a 2to4

Create a Verilog module named if2to4 that represents a 2-to-4 binary decoder using an if-else statement. Create a second module named h3to8 that represents the 3-to-8 binary decoder in Figure 4.15 using two instances of the if2to4 module.

NOT USING (IF,ELSE)

Solution

module if2to4(
input w0,w1,
input En,
output y0,y1,y2,y3
);
reg [3:0] dout ;
wire [1:0] din;
assign din[1]=w1;
assign din[0]=w0;
always @ (En) begin
if(En==0)
begin
if (din==3)
dout = 8;
else if (din==2)
dout = 4;
else if (din==1)
dout = 2;
else
dout = 1;
end
else
begin
dout=0;
end
y0=dout[0];
y1=dout[1];
y2=dout[2];
y3=dout[3];

end

endmodule

module h3to8(
input w0,w1,w2,
input En,
output y0,y1,y2,y3,y4,y5,y6,y7
);

wire en1,en2,w2bar;
assign w2bar=~w2;
assign en1=w2bar & En;
assign en2=w2 & En;
if2to4 u1(.w0(w0),.w1(w1),.En(en1),.y0(y0),.y1(y1),.y2(y2),.y3(y3));
if2to4 u2(.w0(w0),.w1(w1),.En(en2),.y0(y4),.y1(y5),.y2(y6),.y3(y7));

endmodule