Write VHDL code to describe the absolute value circuit from

Write VHDL code to describe the absolute value circuit from Exercise 4, using k = 8 hits. The VHDL module should be called Problem 4. it should accept two 8-bit inputs called A and B, and produce one 8-bit output Y which is the absolute value of A + B. Your solution should include both a schematic and the corresponding VHDL code. You can access the most significant bit of an 8-bit signal S by writing S(7).

Solution

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Problem4 is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); -- 8-bit number
B: in STD_LOGIC_VECTOR (7 downto 0); -- 8-bit number
Y : out STD_LOGIC_VECTOR (7 downto 0)); -- 8 bit result
end Problem4;

architecture Behavioral of Problem4 is
signal x:STD_LOGIC_VECTOR (8 downto 0);
begin
x <= (\'0\' & A) + (\'0\' & B);
Y <=x(7 downto 0);
end Behavioral;