Propose a threestage pipelining Fetch Decode Execute and pro

Propose a three-stage pipelining (Fetch, Decode, Execute) and propose the changes in your proposed scheme and the differences between it and the original five stages pipelining. Draw the three stages illustrating the functions of each stage

Solution

Answer:

Three-stage pipelining;

--> A standard process describes the steps needed for processing to take place. It is called the Fetch - Decode - Execute cycle or sometimes simply called the Fetch-Execute Cycle.

--> In simpler CPUs the instruction cycle is executed sequentially, each instruction being processed before the next one is started.

--> In most modern CPUs the instruction cycles are instead executed concurrently, and often in parallel, through aninstruction pipeline.

--> The CPU decodes the instruction and prepares various areas within the chip in readiness of the next step.

1. FETCH:

--> The first step the CPU carries out is to fetch some data and instructions from main memory then store them in its own internal temporary memory areas.

--> These memory areas are called \'registers\'.

--> The processor will fetch the constant value 0 from the next location in memory before executing the instruction.

--> Memory eventually puts instruction on the data bus.

--> CPU must place an address to the MAR.

--> CPU must activate the tri-state buffer so MAR contents are placed on the address bus.

--> CPU sends R/\\W = 1 and CE = 1 to memory, to indicate it wants to do a read.

--> Memory eventually puts instruction on the data bus.

2) Decode:

--> The next step is for the CPU to make sense of the instruction it has just fetched.

--> This process is called \'decode\'.

--> Recall that operands are arguments to the assembly instruction.

-->The CPU is designed to understand a specific set of commands. These are called the \'instruction set\' of the CPU. Each make of CPU has a different instruction set.

--> The processor will fetch the constant value 0 from the next location in memory before executing the instruction.

In particular, we\'re going to do the following:

a) Get IR_31-26, the opcode

b) Get IR_25-21, which is $rs, the first source register.

c) Get IR_20-16, which is $rt, the second source register.

d) Get IR_15-11, which is $rd, the destination register.

e) Get IR_15-0, the immediate value.

f) Get IR_5-0, the function code.

3)EXECUTE:

--> In the last phase, the processor execute the instruction, it stores 0 in register AX.

--> When the instruction has been decoded, the CPU can carry out the action that is needed. This is called executing the instruction.

--> The CPU is designed to understand a set of instructions the instruction set.

--> This is the part of the cycle when data processing actually takes place.The instruction is carried out upon the data (executed).

--> The result of this processing is stored in yet another register.

--> This instruction involves arithmetic or logic, the Arithmetic Logic Unit is utilized.

--> This is the only stage of the instruction cycle that is useful from the perspective of the end user.

Here 5 types of pipelinings are there:

1) fetch

2) Decode

3) Execute

4) Memory Access

5) Write Back

1) fetch:

-> The first step the CPU carries out is to fetch some data and instructions from main memory then store them in its own internal temporary memory areas.

2) Decode:

--> In each pipeline stage could produce the control signals for the datapath directly from the instruction bits. As a result, very little decoding is done in the stage traditionally called the decode stage.

3) Execute:

--> The Execute stage is where the actual computation occurs.

--> Typically this stage consists of an Arithmetic and Logic Unit, and also a bit shifter.

--> It may also include a multiple cycle multiplier and divider.

4) Memory Access:

-- If data memory needs to be accessed, it is done so in this stage.

--> During this stage, single cycle latency instructions simply have their results forwarded to the next stage.

5) Write Back:

--. In this stage both single cycle and two cycle instructions write their results into the register file.