Complete a VHDL code for a one input and one output sequence

Complete a VHDL code for a one input and one output sequence detector to detect the sequence \"1001\" (overlaps are considered). The state diagram is given below, where the arrows indicate state transitions. State names and output values are given inside state circles. Use the partial code given below.

Solution

architecture behavioral of state_machine is

type state_type is (s0,s1,s2,s3);  --type of state machine.
signal current_s,next_s: state_type;  --current and next state declaration.

begin

process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0;  --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s;   --state change.
end if;
end process;

--state machine process.
process (current_s,x)
begin
  case current_s is
when s0 =>   --when current state is \"s0\"
     if(x =\'0\') then
z <= \'0\';
next_s <= s0;
  else
z <= \'0\';
   next_s <= s1;
     end if;   

when s1 =>;   --when current state is \"s1\"
  if(x =\'0\') then
z <= \'0\';
next_s <= s2;
  else
z <= \'0\';
   next_s <= s1;
   end if;

  when s2 =>     --when current state is \"s2\"
  if(x =\'0\') then
z <= \'0\';
next_s <= s3;
  else
z <= \'0\';
   next_s <= s1;
   end if;


  when s3 =>     --when current state is \"s3\"
  if(x =\'0\') then
z <= \'0\';
next_s <= s0;
  else
z <= \'1\';
   next_s <= s4;
   end if;

when s4 =>     --when current state is \"s4\"
  if(x =\'0\') then
z <= \'0\';
next_s <= s2;
  else
z <= \'0\';
   next_s <= s1;
   end if;
    end case;

end process;

end behavioral;