Write a VerilogVHDL program to model the hardware functional

Write a Verilog/VHDL program to model the hardware functionality of a n-bit wide Booth’s multiplier, where n = 4. Label the multiplicand and multiplier as A and B respectively. Each of these is a n-bit-wide signed binary number in two’s complement format. In addition to these data inputs, there are 3 other inputs: reset, clock, and start. Name the result as P, which is 2n-bit wide. There is another output, ready, which will be asserted high once P is finalized. The reset is synchronous and, if active, will result in a known initial state in the next clock cycle. If reset is not active, and if start is asserted high at the clock edge, then the multiplication process starts in the next clock cycle.

Note: You must use the same input and output names (case-sensitive) and widths in your program as mentioned in this handout.

Result screenshots for each of the following A>0, B>0; A<0, B>0; A>0, B<0; A<0, B<0

Solution

Booth\'s algorithm can be implemented by repeatedly adding (with ordinary unsigned binary addition) one of two predetermined values Aand S to a product P, then performing a rightward arithmetic shift on P. Let m and r be the multiplicand and multiplier, respectively; and let x and y represent the number of bits in m and r.

Example[edit]

Find 3 × (4), with m = 3 and r = 4, and x = 4 and y = 4:

The above mentioned technique is inadequate when the multiplicand is the most negative number that can be represented (e.g. if the multiplicand has 4 bits then this value is 8). One possible correction to this problem is to add one more bit to the left of A, S and P. This then follows the implementation described above, with modifications in determining the bits of A and S; e.g., the value of m, originally assigned to the first x bits of A, will be assigned to the first x+1 bits of A. Below, the improved technique is demonstrated by multiplying 8 by 2 using 4 bits for the multiplicand and the multiplier: