Hello this is my project for Microelectronics Design course

Hello, this is my project for Microelectronics Design course, hope you can help me to solve this problem. Also, if you have some idea about it, please give me some comments , Thank you!

Design Project: Variable Gain Amplifier - session 2, 2016 Problem The aim of this project is, for teams of two students, to design a variable gain amplifier (VGA) in the usual TSMC 0.18m CMOS process used in the course. Parameters for hand calculations. simulation parameters, and layout design rules can be found on the course website Design requirements The design requirements to the amplifier are summarised in figure 1: The amplifier must operate from a dual VDD = 0.9V. Vss =-0.9V power supply; it must have one analogue input, VIN (referred to ground), two digital inputs, gain and reset, and one analogue output, voUT. When reset = 1, the amplifier can be in a reset state where the output will be ignored (this state can be used to cancel internal off-set errors and the likes), when reset = 0, the amplifier must operate in continuous-time with voUT- AvIN, where A is the gain. The gain input must control the gain setting A 2 when gain = 0 and A-4 when gain 1 . The gain input must be ignored when reset = 0 (i.e., it must not be possible to change the gain during the amplification stage. The output voltage error in the amplification stage (deviation from the ideal value. AvOE must be less that 10 mV. All inputs are driven by voltage sources having a source resistance of Rs 10k while the output is loaded by a CL = 1 pF capacitance. You may assume that one bias current is available, of whatever magnitude that suits you. The circuit performance is to be evaluated using the test-setup in figure 2; the circuit itself must contain only NMOS and PMOS transistors, capacitors and resistors Symbol Parameter Positive power supply Negative power supply Bias/reference current Logic high voltage (I) Logic low voltage (0) Load capacitance Source resistance Output voltage error Full-scale output voltage range Ideal gain settings Value 0.9V 0.9 V If desired 0.9V 0.9V IRef VM L. CI HOFS-±0.5 V Figure 1: Amplifier design requirements

Solution

Complementary metal–oxide–semiconductor (CMOS) /sims/ is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. In 1963, while working for Fairchild Semiconductor, Frank Wanlass patented CMOS (US patent 3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS).^[1] The words \"complementary-symmetry\" refer to the fact that the typical design style with CMOS uses complementary and symmetrical pairs of p-typeand n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.^[2]

Two important characteristics of CMOS devices are high noise immunity and low static power consumption.^[3] Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor–transistor logic (TTL) orNMOS logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.

The phrase \"metal–oxide–semiconductor\" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and beyond.^[4]