Answer the following questions based on the circuit schemati

Answer the following questions based on the circuit schematic below. The gate timing parameters are listed as follows. T_clk rightarrow Q = 0.5 ns, t_setup = 0.4ns, t_hold = 0.3ns, t_ln, f = 0.4 ns, t_inv = 0.3 in, t_AND = 0.4 ns, t_OR = 0.5 ns. Calculate the maximum clock frequency. T_max = calculate the maximum external setup time. Calculate the maximum external hold time.

Solution

4.1

t_max=(0.4+0.4+0.5)-0.4 =====1.4ns

4.2

maximum external setup tome

The calculation for External Setup time for pad-to-register paths: Tsu(ext) = T(data_path) + Tsu(int) - T(clock_path) T(data_path) = maximum data path delay

0.5ns(ans)

Th(int) = hold time of an internal register. T(clock_path) = maximum clock path delay.

0.3ns as givn in question

4.3