A common manufacturing defect which can occur in the early s

A common manufacturing defect which can occur in the early stages of the development of a new processor
is a stuck at 1 or stuck at 0 defect. A stuck at 1 defect means a bit, which should be able to be set (to 1) or
cleared (to 0) is stuck at 1, i.e., it always remains set. I will let you figure out what a stuck at 0 defect is. Suppose we
are manufacturing a MIPS32 processor and two defects occur causing the RegDst control signal to be stuck at 1 and
the MemToReg control signal to be stuck at 0. Suppose we do not know that yet, but we discover that the execution of
the instruction which is encoded as 0x8D79_9C00 causes something to happen other than what we expected. (a)
What MIPS assembly language instruction is this? Write any numbers in decimal. (b) Explain in English what the
instruction should do, assuming no defects. (c) Explain what the result of executing this instruction actually will do,
with the defects.

Solution

The MIPS R2000 CPU has 32 registers. 31 of these are general-purpose registers that can be used in any of the instructions. The last one, denoted register zero, is defined to contain the number zero at all times. Even though any of the registers can theoretically be used for any purpose, MIPS programmers have agreed upon a set of guidelines that specify how each of the registers should be used. Programmers (and compilers) know that as long as they follow these guidelines, their code will work properly with other MIPS code. Symbolic Name Number Usage zero 0 Constant 0. at 1 Reserved for the assembler. v0 - v1 2 - 3 Result Registers. a0 - a3 4 - 7 Argument Registers 1 · · · 4. t0 - t9 8 - 15, 24 - 25 Temporary Registers 0 · · · 9. s0 - s7 16 - 23 Saved Registers 0 · · · 7. k0 - k1 26 - 27 Kernel Registers 0 · · · 1. gp 28 Global Data Pointer. sp 29 Stack Pointer. fp 30 Frame Pointer. ra 31 Return Address

If an instruction description begins with an , then the instruction is not a member of the native MIPS instruction set, but is available as a pseudoinstruction. The assembler translates pseudoinstructions into one or more native instructions

Op Operands Description abs des, src1 des gets the absolute value of src1. add(u) des, src1, src2 des gets src1 + src2. and des, src1, src2 des gets the bitwise and of src1 and src2. div(u) src1, reg2 Divide src1 by reg2, leaving the quotient in register lo and the remainder in register hi. div(u) des, src1, src2 des gets src1 / src2. mul des, src1, src2 des gets src1 × src2. mulo des, src1, src2 des gets src1 × src2, with overflow. mult(u) src1, reg2 Multiply src1 and reg2, leaving the low-order word in register lo and the high-order word in register hi. neg(u) des, src1 des gets the negative of src1. nor des, src1, src2 des gets the bitwise logical nor of src1 and src2. not des, src1 des gets the bitwise logical negation of src1. or des, src1, src2 des gets the bitwise logical or of src1 and src2. rem(u) des, src1, src2 des gets the remainder of dividing src1 by src2. rol des, src1, src2 des gets the result of rotating left the contents of src1 by src2 bits. ror des, src1, src2 des gets the result of rotating right the contents of src1 by src2 bits. sll des, src1, src2 des gets src1 shifted left by src2 bits. sra des, src1, src2 Right shift arithmetic. srl des, src1, src2 Right shift logical. sub(u) des, src1, src2 des gets src1 - src2. xor des, src1, src2 des gets the bitwise exclusive or of src1 and src2.