VHDL programming assignment implement a generic Nbit updown

VHDL programming assignment:

implement a generic N-bit up-down counter.

Solution

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- up/down counter with limits that uses one GENERIC entity up_down_counter3_top is Generic (CLK_BIT : INTEGER := 3); Port ( CLK : in STD_LOGIC; DIR : in STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0)); end up_down_counter3_top; architecture Behavioral of up_down_counter3_top is signal clk_div : STD_LOGIC_VECTOR (CLK_BIT downto 0); signal count : STD_LOGIC_VECTOR (7 downto 0); begin -- clock divider process (CLK) begin if (CLK\'Event and CLK = \'1\') then clk_div <= clk_div + \'1\'; end if; end process; -- up/down counter process (clk_div(CLK_BIT)) begin if (clk_div(CLK_BIT)\'Event and clk_div(CLK_BIT) = \'1\') then if (DIR = \'1\') then -- count up to 15 then stop while (count < 15) loop count <= count + \'1\'; -- count up end loop; else -- count down to 0 then stop while (count > 0) loop count <= count - \'1\'; -- count down end loop; end if; end if; end process; LED <= not count; end Behavioral;