3 PRELIMINARY LAB 31 For the circuit in Figure 2 assume VDD

3. PRELIMINARY LAB 3.1. For the circuit in Figure 2 assume VDD = Vss = 5 V. For both M1 and M2 assume VT = 1 W/L*ka = 0.8 mA/V2 and ignore finite output impedance. Estimate R required to have drain current IDI equal to 250 A. Find the corresponding value of gate-to-source voltage of M1 and M2. Determine the minimum value of VDD2 for M2 to remain in saturation. 3.2. Consult with ALD1105 datasheet and build a basic LEVEL 1 Spice models for corresponding NMOS and PMOS FETs. Hint: Use model of 2N7000 from lab I as a template and adjust its parameters according to the following lines from datasheet: Test Max Unit Gate Theeshoild VT oltage 040.7-1.0V Gts Output Gos 200 40 3.3. For the circuit (A fid RD to yield DC voltage at output (drain of M1) equal to zero. Using hand calculations estimate the maximum amplitude of the undistorted output sine wave. Using PSpice find the value of the voltage gain at lkHz. Show the input and output signals on the same plot. Using PSpice estimate the maximum amplitude of the undistorted output sine wave. Compare with the results of hand calculations. 3.4. For the circuit (B) use PSpice to find the value of the voltage gain at 1kHz. Show the input and output signals on the same plot (determine the DC voltage at the output and subtract it from output waveform to plot both input and output on the same graph). Compare with the results of hand calculations. Hint: start with the input amplitude of 50 mV and reduce it until output sine wave is not distorted. 3.5. Remove 1 F capacitor from circuit (B) and repeat finding voltage gain at 1 kHz using PSpice. Compare with the results of 3.4. Explain your observations. ALD1105P ALD1105 ALDI 105P ALDI 105P ALD1105N ALD1105N FREO 1k 1u 5V

Solution

ID1=259 micro A

Vs=source voltage =-vss=-5 v

VGs=VG-Vs=VG+5

Now : ID1=kn*(w/L)(VGS-VT)^2/2

250=0.8(VG+4)^2/2

(VG+4)^2=0.79

VG=-4.79, -3.11 v

As VGS>VT, hence VG=-3.11 v

Now VD1= drain voltage of M1=VG=-3.11 v

R=(VDD-VD1)/ID1=8.11/250=32.44 k ohm

M2 will be in saturation if VDD2>=(VG-vt)

VDD2>=-4.11 v

VDD2(minimum)=-4.11 v