Logic diagram for twobit by twobit binary multiplier Write t

Logic diagram for two-bit by two-bit binary multiplier Write the Entity Declaration for the schematic shown above. LIBRARY IEEE; USE IEEE.STD_LOGIC.1164.ALL; ENTITY comp IS END comp;

Solution

--- Firstly, define the Half-adder(HA) that we need for the multiplier ---- library ieee; use ieee.std_logic_1164.all; entity halfadder is port( A, B : in std_logic; SUM, CO : out std_logic); end halfadder; architecture ha of halfadder is begin SUM <= A xor B; CO <= A and B; end ha; ----------- Definition of the multiplier starts from here ------------- library ieee; use ieee.std_logic_1164.all; entity multiplier2x2 is port( A0, A1, B0, B1 : in std_logic; C0, C1, C2,C3 : out std_logic); end multiplier2x2; architecture mult2x2 of multiplier2x2 is component halfadder is port( A, B : in std_logic; SUM, CO : out std_logic); end component; signal n1, n2, n3, n4 : std_logic; begin C0 <= A0 and B0; n1 <= B1 and A0; n2 <= B0 and A1; n3 <= B1 and A1; U1 : halfadder port map(n1, n2, C1, n4); U2 : halfadder port map(n3, n4, C3, C2) ; end halfAdder;