With the help of the template in Hall Appendix A1 show the L

With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction ADDEQ R3, R7, R9. (Remember shift bits all 0\'s) With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction EORSNE R1, R5, R4. (Remember shift bits all 0\'s) With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction SUBSEQ R1, R2, R3. (Remember shift bits all 0\'s) With the help of the template in Hall Appendix A1, show the labeled machine code for the XScale instruction ANDNE R7, R4, R5. (Remember shift bits all 0\'s) For the ARM ANDEQ R3, R7, R9 instruction, the 4-bit condition code that the assembler would insert in the 32-bit code for this instruction is __ 0000 _______.

Solution

Rd,Rm,Rn are three registers using which you are performing desired operation.

Any instruction will be in form of

Example: ANDEQ R3,R7,R9

Write opcode for ANDEQ

Rd=R3,Rn=R7,Rm=R9

Rd=0011,Rn=0111,R9=1001

Similarly SUBEQ R3,R5,R6

Rd=R3,Rn=R5,Rm=R6

S is the status of condition code flags which is indicated in instruction

Ex: SUBSEQ R3,R7,R9 indicates s=1 because S is present in instruction.

SUBEQ R3,R7,R9 s=0.

COND indicates type of instruction.

Ex: data transfer instruction etc...

COND=0000 for data transfer instruction.

Op which is opcode ,based on operation it differs

For AND operation op=0000.

I hope this answer definitely help you.