Write the VHDL code entity and architecture to implement the

Write the VHDL code (entity and architecture) to implement the 1 -bit half adder shown in Fig. 4(a)(ii). Write the VHDL code (entity and architecture) to implement the 1 -bit full adder shown in Fig. 4(a)(ii). The logic diagram of a ripple carry adder is shown in Fig. 4(a)(i). It consists of one 1-bit half adder and three 1-bit full adders (Fig. 4(a)(ii)). A, B and D are 4-bit numbers. Use the 1-bit half adder and 1-bit full adder as components to write the VHDL code (entity and architecture) to implement the ripple carry adder using the appropriate design approach.

Solution

-- Half adder

library IEEE;

use IEEE.std_logic_1164.all;

entity onebithalfadder is

port (I1, I2, : in std_logic;

Sum, Cout : out std_logic);

end onebithalfadder;

architecture behavior of onebitfulladder is

signal S1, S2, S3 : std_logic;

begin

Sum <= I1 xor I2;

Cout <= I1 and I2;

end behavior;

--Full adder

library IEEE;

use IEEE.std_logic_1164.all;

entity onebitfulladder is

port (I11, I2, Cin : in std_logic;

Sum, Cout : out std_logic);

end onebitfulladder;

architecture behavior of onebitfulladder is

signal S1, S2, S3 : std_logic;

begin

result <= I1 xor I2 xor Cin;

S1 <= I1 and I2;

S2 <= I1 and Cin;

S3 <= Cin and I2;

Cout <= S1 or S2 or S3;

end behavior;

-- Ripple carry adder

ibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ripple_Adder is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

D : out STD_LOGIC_VECTOR (3 downto 0);

C4 : out STD_LOGIC);

end Ripple_Adder;

architecture Behavioral of ripple_Adder is

component onebitfulladder

Port ( I1 : in STD_LOGIC;

I2 : in STD_LOGIC;

Cin : in STD_LOGIC;

Sum : out STD_LOGIC;

Cout : out STD_LOGIC);

end component;

component onebithalfadder

Port ( I1 : in STD_LOGIC;

I2 : in STD_LOGIC;

Sum : out STD_LOGIC;

Cout : out STD_LOGIC);

end component;

signal c1,c2,c3: STD_LOGIC;

begin

--port mapping of one half adder and three full adders

HA1: onebithalfadder port map( A(0), B(0), D(0), c1);

FA1: onebitfulladder port map( A(1), B(1), c1, D(1), c2);

FA2: onebitfulladder port map( A(2), B(2), c2, D(2), c3);

FA3: onebitfulladder port map( A(3), B(3), c3, D(3), C4);

end Behavioral;