Convert VHDL to Verilog entity cpu is port clkcpu stdlogic r

Convert VHDL to Verilog

entity cpu is

port (clk_cpu: std_logic;

rst_cpu: in std_logic;

input_cpu: in std_logic_vector(7 downto 0);

output_cpu: out std_logic_vector(7 downto 0));

end cpu;

architecture structure of cpu is

component ctrl

port (clk_ctrl: in std_logic;

rst_ctrl: in std_logic;

muxsel_ctrl: out std_logic_vector(1 downto 0);

imm_ctrl: out std_logic_vector(7 downto 0);

accwr_ctrl: out std_logic;

rfaddr_ctrl: out std_logic_vector(2 downto 0);

rfwr_ctrl: out std_logic;

alusel_ctrl: out std_logic_vector(2 downto 0);

shiftsel_ctrl: out std_logic_vector(1 downto 0);

outen_ctrl: out std_logic;

zero_ctrl: in std_logic;

positive_ctrl: in std_logic);

end component;

component dp

port(clk_dp: in std_logic;

rst_dp: in std_logic;

muxsel_dp: in std_logic_vector(1 downto 0);

imm_dp: in std_logic_vector(7 downto 0);

input_dp: in std_logic_vector(7 downto 0);

accwr_dp: in std_logic;

rfaddr_dp: in std_logic_vector(2 downto 0);

rfwr_dp: in std_logic;

alusel_dp: in std_logic_vector(2 downto 0);

shiftsel_dp: in std_logic_vector(1 downto 0);

outen_dp: in std_logic;

zero_dp: out std_logic;

positive_dp: out std_logic;

output_dp: out std_logic_vector(7 downto 0));

end component;

signal C_immediate: std_logic_vector(7 downto 0); --SIGNAL D_immediate: std_logic_vector(7 DOWNTO 0);

signal C_accwr,C_rfwr,C_outen,C_zero,C_positive: std_logic;

signal C_muxsel,C_shiftsel: std_logic_vector(1 downto 0);

signal C_rfaddr,C_alusel: std_logic_vector(2 downto 0);

begin

U0: ctrl port map(clk_cpu,rst_cpu,C_muxsel,C_immediate,C_accwr,C_rfaddr,C_rfwr,C_alusel

,C_shiftsel,C_outen,C_zero,C_positive);

U1: dp port map(clk_cpu,rst_cpu,C_muxsel,C_immediate,input_cpu,C_accwr,C_rfaddr,C_rfwr

,C_alusel,C_shiftsel,C_outen,C_zero,C_positive,output_cpu);

end structure;

Convert the VHDL code to Verilog

Solution

module cpu(clk_cpu,rst_cpu,input_cpu,output_cpu);
input clk_cpu;
input rst_cpu;
input [7:0]input_cpu;
output [7:0]output_cpu;
wire [7:0] C_immediate; --SIGNAL D_immediate: std_logic_vector(7 DOWNTO 0);
wire C_accwr,C_rfwr,C_outen,C_zero,C_positive;
wire [1:0] C_muxsel,C_shiftsel;
wire [2:0] C_rfaddr,C_alusel;
begin
ctrl U0(clk_cpu,rst_cpu,C_muxsel,C_immediate,C_accwr,C_rfaddr,C_rfwr,C_alusel,C_shiftsel,C_outen,C_zero,C_positive);
dp U1(clk_cpu,rst_cpu,C_muxsel,C_immediate,input_cpu,C_accwr,C_rfaddr,C_rfwr,C_alusel,C_shiftsel,C_outen,C_zero,C_positive,output_cpu);
      
endmodule

module ctrl(clk_ctrl,rst_ctrl,muxsel_ctrl,imm_ctrl,accwr_ctrl,rfaddr_ctrl,rfwr_ctrl,alusel_ctrl,shiftsel_ctrl,outen_ctrl,zero_ctrl,positive_ctrl);

input clk_ctrl,rst_ctrl,zero_ctrl,positive_ctrl;
output [1:0]muxsel_ctrl,shiftsel_ctrl;
output [2:0]rfaddr_ctrl,alusel_ctrl;
output [7:0]imm_ctrl;

//operation of module ctrl will code here

endmodule;

module dp(clk_dp,rst_dp,muxsel_dp,imm_dp,input_dp,accwr_dp,rfaddr_dp,rfwr_dp,alusel_dp,shiftsel_dp,outen_dp,zero_dp,positive_dp,output_dp);

input clk_dp,rst_dp,accwr_dp,rfwr_dp,outen_dp;
input [1:0]muxsel_dp,shiftsel_dp;
input [2:0]rfaddr_dp,alusel_dp;
input [7:0]imm_dp,input_dp;
output zero_dp;
output [7:0]output_dp;

//operation of module dp will code here

endmodule