Create a verilog module named debouncev based on the diagram

Create a verilog module named \"debounce.v\" based on the diagram below. Use case statements in an always block to de?ne state-speci?c behaviors to fill in the code below. You will need to declare reg signals for \"state\" and \"nextState\", and I/Os for \"b\", \"d\" and \"clk\". Your intended behavior is to execute one increment per button press. A complete button press involves pressing and then releasing the button. This protocol is modeled by the Mealy-type FSM shown below. In this model, we use the convention “b=1” to indicate a input conditional evaluation (i.e. if b==1 then...), and we use “d:=1” to indicate an output assignment that sets a new value for d.

Solution

`timescale 1ns/1ns

module debounce (
clock,start,b,
d);

input clock;
input start;
input b;
tri0 start;
tri0 b;
output d;
reg d;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter waiting=0,pressed=1,held=2,released=3;

always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end

always @(fstate or start or b)
begin
if (~start) begin
reg_fstate <= waiting;
d <= 1\'b0;
end
else begin
d <= 1\'b0;
case (fstate)
waiting: begin
if (~(b))
reg_fstate <= waiting;
else if (b)
reg_fstate <= pressed;

if (~(b))
d <= 1\'b0;
else if (b)
d <= 1\'b0;
// Inserting \'else\' block to prevent latch inference
else
d <= 1\'b0;
end
pressed: begin
if (~(b))
reg_fstate <= waiting;
else if (b)
reg_fstate <= held;

if (b)
d <= 1\'b0;
else if (~(b))
d <= 1\'b0;
// Inserting \'else\' block to prevent latch inference
else
d <= 1\'b0;
end
held: begin
if (b)
reg_fstate <= held;
else if (~(b))
reg_fstate <= released;

if (~(b))
d <= 1\'b0;
else if (b)
d <= 1\'b0;
// Inserting \'else\' block to prevent latch inference
else
d <= 1\'b0;
end
released: begin
if (~(b))
reg_fstate <= waiting;
else if (b)
reg_fstate <= held;

if (b)
d <= 1\'b0;
else if (~(b))
d <= 1\'b1;
// Inserting \'else\' block to prevent latch inference
else
d <= 1\'b0;
end
default: begin
d <= 1\'bx;
$display (\"Reach undefined state\");
end
endcase
end
end
endmodule // debounce