Shown below are three separate and unrelated code sequences

Shown below are three separate and unrelated code sequences a), b) and c). Each sequence executes seperately. Assume that in-order issue and out of order completion are used for each sequence running on a superscalar version of our MIPS processor.

Solution

I0 & I1:
I0->meaning $4=$5+$9
I1->meaning $9=$4-$5
i) RAW dependency.
Register 4. I0 is writing and then I1 is reading
ii) WAR dependency
Register 9. I0 is reading and then I1 is writting
I0&I2:
i) RAW dependency.
Register 4. I0 is writing and then I2 is reading
I1&I2:
i) RAW dependency.
Register 9. I1 is writing and then I2 is reading
I3&I4:
i) WAR dependency.
Register 9.I3 is reading and then I4 is writing
I3&I5:
i) WAW dependency
Register 4. I3 is writting and I5 is writting
I4&I5: none
I6&I7:
i) WAR dependency
Register 9. I6 is reading and I7 is writting
I6&I8:
i)RAW dependency
Register 4 . I6 is writting and then I8 is reading
I7&I8:
i)RAW dependency
Register 9 . I7 is writting and then I8 is reading
ii) WAR dependency
Register 11. I7 is reading and I8 is writting