each gate in the circuit has a tplh and a tplh of 4ns if a p

Solution

The operation of a CMOS NAND gate is as follows: A B Q1 Q2 Q3 Q4 Output LOW LOW ON ON OFF OFF HIGH LOW HIGH ON OFF OFF ON HIGH HIGH LOW OFF ON ON OFF HIGH HIGH HIGH OFF OFF ON ON LOW

The main use of the open-collector gates is to be wired together to form a wired-AND configuration. • Open-collector outputs are tied directly together which results in the logical AND of the outputs. • The equivalent of an AND gate can be formed by simply connecting the outputs. • It is especially convenient when large numbers of signals need to be ANDed. Using the regular gates, if a gate having a HIGH output (5V) is connected to another gate having a LOW output (0V), you would have a direct short circuit, causing either or both gates to burn out

Open-collector devices allow for the connection of outputs from several different circuits. Outputs can be tied together without causing damage to the internal circuitry because open-collector do not have the output stage connected to VCC. In order to get the proper HIGH and LOW logic levels out of the circuit, an external pull-up resistor must be connected to VCC from the collector of Q3. When Q3 is off, the output is pulled up to VCC through the external resistor. When Q3 is on, the output is connected to near-ground through the saturated transistor.