Using the design procedures taught in class derive synchrono

Using the design procedures taught in class, derive synchronous sequential circuits for the following as specified by the following requirements. Each circuit has a single input line x and a single output line z.

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Solution

Rule Adjacencies 1a EK, EL, KL 1c GJ, IJ 2 AB, CD, DF, GH, HI, IJ, EK, EL, KL 3 EK, EL (c) y1\'y2\'y3\'y4\' y1y2y3y4 x = 0 x = 1 R 0000 1100 1110 E 0001 0000 0000 K 0011 0000 0000 0010 xxxx xxxx C 0100 1011 1010 L 0101 0000 0000 F 0111 1000 1001 D 0110 1010 1000 I 1000 0101 0001 J 1001 0001 0001 G 1011 0001 0011 H 1010 0011 0101 A 1100 0100 0110 1101 xxxx xxxx 1111 xxxx xxxx B 1110 0110 0

x = 0 x = 1 y1y2 1 1 1 × 1 × × 1 1 × × × 1 1 00 01 11 10 00 01 11 10 10 11 01 00 y3y4 y1y2 x = 0 x = 1 y1y2 1 × × × 1 1 1 1 1 × × 1 × 1 00 01 11 10 00 01 11 10 10 11 01 00 y3y4 y1y2 x = 0 x = 1 y1y2 1 1 × 1 × 1 × 1 1 × 1 1 × 1 ×

The transition table resulting from the adjacency map is shown in Figure 19c. Since four state variables imply 16 possible states, and there are actually only 13, three of the state variable combinations do not correspond to states of the machine. Hence, we don’t care what the next states resulting from such nonexistent present states will be