Outvecs value is determined by the following criterion When

Outvec\'s value is determined by the following criterion: When opcode is 00, outvec and invec are the same When opcode is 01, the even bits of invec are inverted. For example, if invec =1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 and opcode was 01, then outvec = 0101010101010101 When opcode is 10, the odd bits of invec are inverted. When opcode is 11, every other even bit, starting with 0, is inverted.

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity oper is
Port ( Invec : in Bit_VECTOR (0 downto 15);
Opcode : in Bit_VECTOR (0 downto 1);
Outvec : out Bit_VECTOR (0 downto 15));
end oper;

architecture Behavioral of oper is

begin
process(Opcode)
begin
if Opcode=\"0O\" then
Outvec <= Invec;
elsif Opcode=\"01\" then
L1: for i in 1 to 16 loop
if i mod 2=\"1\" then
Outvec(i-1)<=Invec(i-1);
else
Outvec(i-1)<=not Invec(i-1);
end if;
end loop L1;
elsif Opcode=\"10\" then
L2: for i in 1 to 16 loop
if(i mod 2=\"1\") then
Outvec(i-1)<=not Invec(i-1);
else
Outvec(i-1)<=Invec(i-1);
end if;
end loop L2;
else
L3: for i in 1 to 16 loop
if(i mod 2=\"1\") then
Outvec(i-1)<=not Invec(i-1);
else
if (Invec(i-1)=\"1\") then
Outvec(i-1)<=Invec(i-1);
else
Outvec(i-1)<=not Invec(i-1);
end if;
end if;
end loop L3;
end if;
end process;
end Behavioral;