8 points Assume that you have four 4 ROM chips organized as

(8 points) Assume that you have four (4) ROM chips organized as 16Kx8 with signals OE, CE, A13.0, D.0, and Vpp (similar to one shown in figure 14-14 on page 432). Assume you would like to implement all ROM externally, show the connectivity between the 8051 and those chips to allow the implementation of a complete 64K ROM address space. Make sure to show all signals (i.e. PSEN, address lines, etc) to implement this system correctly (i.e. as shown in figure 14-14). You should also indicate the addresses associate each external ROM chip. 13.0, D^7.0, and Vpp (simlar to one shown in figure

Solution

The last part is to use it from the application. Typically I have a header file like the one below where I have the addresses defined:

/**

* \\file

* \\brief Interface for the Non-Volatile-Memory

* \\author Erich Styger

*

* This provides an interface to store and retrieve data from the on-chip memory.

*/

#ifndef CONFIGNVM_H_

#define CONFIGNVM_H_

#define NVMC_FLASH_START_ADDR    0x1FC00 /* NVRM_Config, start address of configuration data in flash */

#define NVMC_FLASH_ERASED_UINT8 0xFF

#define NVMC_FLASH_ERASED_UINT16 0xFFFF

#define NVMC_REFLECTANCE_DATA_START_ADDR (NVMC_FLASH_START_ADDR)

#define NVMC_REFLECTANCE_DATA_SIZE        (8*2*2) /* maximum of 8 sensors (min and max) values with 16 bits */

#define NVMC_REFLECTANCE_END_ADDR         (NVMC_REFLECTANCE_DATA_START_ADDR+NVMC_REFLECTANCE_DATA_SIZE)

#define NVMC_SUMO_DATA_START_ADDR         (NVMC_REFLECTANCE_END_ADDR)

#define NVMC_SUMO_DATA_SIZE               (4) /* 4 bytes of data */

#define NVMC_SUMO_END_ADDR                (NVMC_SUMO_DATA_START_ADDR+NVMC_SUMO_DATA_SIZE)

uint8_t NVMC_SaveReflectanceData(void *data, uint16_t dataSize);

void *NVMC_GetReflectanceData(void);

uint8_t NVMC_SaveSumoData(void *data, uint16_t dataSize);

void *NVMC_GetSumoData(void);

#endif /* CONFIGNVM_H_ */

 (8 points) Assume that you have four (4) ROM chips organized as 16Kx8 with signals OE, CE, A13.0, D.0, and Vpp (similar to one shown in figure 14-14 on page 43

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