You are given tristate buffers with an enable input which pu

You are given tri-state buffers with an enable input which puts output in high state when enable inpu is logic 0 Design a 8:1 multiplexer using tri-statc gates and any additional components you want

Solution

Answer:

module mux (a, b, c, d, e, f, g, h s, o);

input a,b,c,d, e, f, g, h;
input [7:0] s;
output o;

assign o = s[3] ? g :1\'bz;
assign o = s[2] ? f :1\'bz;
assign o = s[1] ? e :1\'bz;
assign o = s[0] ? d :1\'bz;
assign o = s[3] ? d :1\'bz;
assign o = s[2] ? c :1\'bz;
assign o = s[1] ? b :1\'bz;
assign o = s[0] ? a :1\'bz;

endmodule