Homework SourseConvert VHDL to Verilog entity regfile is portclkreg in stdl
Convert VHDL to Verilog
entity reg_file is
port(clk_reg: in std_logic;
wr_reg: in std_logic;
addr_reg: in std_logic_vector(2 downto 0);
input_reg: in std_logic_vector(7 downto 0);
output_reg: out std_logic_vector(7 downto 0));
end reg_file;
architecture reg_file of reg_file is
type mem is array (0 to 7) of std_logic_vector(7 downto 0);
signal d:mem;
begin
process(clk_reg,wr_reg,addr_reg)
begin
if(clk_reg\'event and clk_reg = \'1\') then
if(wr_reg=\'1\') then
if(addr_reg=\"000\") then
d(0)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"001\") then
d(1)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"010\") then
d(2)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"011\") then
d(3)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"100\") then
d(4)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"101\") then
d(5)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"110\") then
d(6)<=input_reg;
output_reg<=input_reg;
elsif(addr_reg=\"111\") then
d(7)<=input_reg;
output_reg<=input_reg;
end if;
else
if(addr_reg=\"000\") then
output_reg<=d(0);
elsif(addr_reg=\"001\") then
output_reg<=d(1);
elsif(addr_reg=\"010\") then
output_reg<=d(2);
elsif(addr_reg=\"011\") then
output_reg<=d(3);
elsif(addr_reg=\"100\") then
output_reg<=d(4);
elsif(addr_reg=\"101\") then
output_reg<=d(5);
elsif(addr_reg=\"110\") then
output_reg<=d(6);
elsif(addr_reg=\"111\") then
output_reg<=d(7);
end if;
end if;
end if;
end process;
end reg_file;
Convert the VHDL code to Verilog
Solution
module reg_file(clk_reg,wr_reg,addr_reg,input_reg,output_reg);
input clk_reg,wr_reg;
input [2:0]add_reg;
input[7:0]input_reg;
output[7:0]output_reg;
begin
process(clk_reg,wr_reg,addr_reg)
always @(wr_eg,clk_reg=>1)
3\'000=d(0);
3\'001=d(1);
3\'010=d(2);
3\'011=d(3);
3\'100=d(4);
3\'101=d(5);
3\'110=d(6);
3\'111=d(7);
end process;
always @(add_reg);
3\'000=d(0);
3\'001=d(1);
3\'010=d(2);
3\'011=d(3);
3\'100=d(4);
3\'101=d(5);
3\'110=d(6);
3\'111=d(7);
end module
