Write complete VHDL code as a clock divideby2 function The n

Write complete VHDL code as a clock divideby2 function. The new clock signal should be called clkhalf\'\' and the input clock signal is called clk. Simulate your design by including a testbench.

Solution

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.numeric_std.ALL;

entity Clock_Divider_by_two is

port ( clk,reset: in std_logic;

clkhalf: out std_logic);

end Clock_Divider_by_two;

architecture bhv of Clock_Divider_by_two is

signal count: integer:=0;

signal temp : std_logic := \'1\';

begin

process(clk,reset)

begin

if(reset=\'0\') then

count<=0;

temp<=\'1\';

elsif(clk\'event and clk=\'1\') then

count <=count+1;

if (counter = 25000) then

temp <= NOT temp;

count <= 0;

end if;

end if;

clkhalf <= temp;

end process;

end bhv;