This project is to design and simulate an ALU module using V

This project is to design and simulate an ALU module using VHDL. Design an ALU module base on the following functional block. The Data_in bus and Data_out bus are 32-bit wide. The V is the overflow signal. Done signal should last at least one clock cycle when the operation id done. The St Signal is the start signal for a specific Op Code. Simulate your ALU design with Modelsim. Show the proper simulation results for all three arithmetic operations.

Solution

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux1_4to1 is Port ( a,b,c,d:in STD_LOGIC;

s: in STD_LOGIC_VECTOR(1 downto 0);

y: out STD_LOGIC); end mux1_4to1;

architecture bhv_mux1_4to1 of mux1_4to1 is

begin

process(s,a,b,c,d)

begin

case s is when \"00\" => y<=a;

when \"01\" => y<=b;

when \"10\" => y<=c;

when \"11\" => y<=d;

when others => y<=\'Z\';

end case;

end process;

end bhv_mux1_4to1;

--------------------------------------

----------------------- SELECTION MUX 2 TO 1 (33 BIT I/O) ----------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity

mux33_2to1 is

Port ( a:in STD_LOGIC_VECTOR (32 downto 0);

b:in STD_LOGIC_VECTOR (32 downto 0);

s: in STD_LOGIC;

y: out STD_LOGIC_VECTOR (32 downto 0));

end mux33_2to1;

architecture bhv_mux33_2to1 of mux33_2to1 is

begin

process(s,a,b)

begin

case s is when \'0\' => y<=a;

when \'1\' => y<=b;

when others => y<=\"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ\";

end case;

end process;

end bhv_mux33_2to1;

-------------------------------------------------------------------------------- ----------------------------------- FULL ADDER ---------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

cout : out STD_LOGIC);

end full_adder;

architecture bhv_full of full_adder is

begin sum <= (a xor b) xor cin;

cout <= (a and b) or ((a xor b) and cin);

end bhv_full;

-------------------------------------------------------------------------------- ---------------------------------- 4BIT ADDER ------------------------------

----

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_4bit is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

cin : in STD_LOGIC;

sum : out STD_LOGIC_VECTOR (3 downto 0);

carry : out STD_LOGIC);

end adder_4bit;

architecture bhv_4bit of adder_4bit is component full_adder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

cout : out STD_LOGIC);

end component;

signal s:STD_LOGIC_VECTOR (2 downto 0);

begin p1:full_adder port map(a(0),b(0),cin,sum(0),s(0));

p2:full_adder port map(a(1),b(1),s(0),sum(1),s(1));

p3:full_adder port map(a(2),b(2),s(1),sum(2),s(2));

p4:full_adder port map(a(3),b(3),s(2),sum(3),carry);

end bhv_4bit;

----------------------------------------------

---------------------------------- 32BIT ADDER ---------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity

Adder_32bit is Port

( i_a : in STD_LOGIC_VECTOR (31 downto 0);

i_b : in STD_LOGIC_VECTOR (31 downto 0);

c_in : in STD_LOGIC;

result : out STD_LOGIC_VECTOR (32 downto 0));

end Adder_32bit;

architecture

bhv_adder_32 of Adder_32bit is component adder_4bit is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

cin : in STD_LOGIC;

sum : out STD_LOGIC_VECTOR (3 downto 0);

carry : out STD_LOGIC); end component;

signal s:STD_LOGIC_VECTOR (6 downto 0);

begin s1:adder_4bit port map(i_a(3 downto 0),i_b(3 downto 0),c_in,result(3 downto 0),s(0));

s2:adder_4bit port map(i_a(7 downto 4),i_b(7 downto 4),s(0),result(7 downto 4),s(1));

s3:adder_4bit port map(i_a(11 downto 8),i_b(11 downto 8),s(1),result(11 downto 8),s(2));

s4:adder_4bit port map(i_a(15 downto 12),i_b(15 downto 12),s(2),result(15 downto 12),s(3));

s5:adder_4bit port map(i_a(19 downto 16),i_b(19 downto 16),s(3),result(19 downto 16),s(4));

s6:adder_4bit port map(i_a(23 downto 20),i_b(23 downto 20),s(4),result(23 downto 20),s(5));

s7:adder_4bit port map(i_a(27 downto 24),i_b(27 downto 24),s(5),result(27 downto 24),s(6));

s8:adder_4bit port map(i_a(31 downto 28),i_b(31 downto 28),s(6),result(31 downto 28),result(32));

end bhv_adder_32;

-------------------------------------------------------------------------------- ------------------------------------ 32BIT AND -------------------------------

-- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity

AND_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0);

i_b : in STD_LOGIC_VECTOR (31 downto 0);

result : out STD_LOGIC_VECTOR (32 downto 0));

end AND_32bit;

architecture

Bhv_and_32bit of AND_32bit is begin result(31 downto 0)<=i_a(31 downto 0) and i_b(31 downto 0);

result(32)<=\'Z\';

end Bhv_and_32bit;

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

IEEE.STD_LOGIC_UNSIGNED.ALL;

entity

OR_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0);

i_b : in STD_LOGIC_VECTOR (31 downto 0);

result : out STD_LOGIC_VECTOR (32 downto 0));

end OR_32bit;

architecture

Bhv_or_32bit of OR_32bit is begin result(31 downto 0)<=i_a(31 downto 0) or i_b(31 downto 0);

result(32)<=\'Z\';

end Bhv_or_32bit;

-------------------------------------------------------------------------------- ------------------------------------ 32BIT XOR ------------------------------

--- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity

XOR_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0);

i_b : in STD_LOGIC_VECTOR (31 downto 0);

result : out STD_LOGIC_VECTOR (32 downto 0));

end XOR_32bit;

architecture Bhv_xor_32bit of XOR_32bit is begin result(31 downto 0)<=i_a(31 downto 0) xor i_b(31 downto 0); result(32)<=\'Z\';

end Bhv_xor_32bit;

-------------------------------------------------------------------------------- ------------------------------------ 32BIT NOT --------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NOT_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0);

result : out STD_LOGIC_VECTOR (32 downto 0)); end NOT_32bit;

architecture Bhv_not_32bit of NOT_32bit is begin result(31 downto 0)<=not i_a(31 downto 0); result(32)<=\'Z\'; end Bhv_not_32bit; -------------------------------------------------------------------------------- ----------------------------------- RIGHT SHIFT -------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity R_Shift_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end R_Shift_32bit; architecture bhv_rshift_32 of R_Shift_32bit is begin result(30 downto 0)<=i_a(31 downto 1); result(31)<=c_in; result(32)<=i_a(0); end bhv_rshift_32; -------------------------------------------------------------------------------- ------------------------------------ LEFT SHIFT -------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity L_Shift_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end L_Shift_32bit; architecture bhv_lshift_32 of L_Shift_32bit is begin result(31 downto 1)<=i_a(30 downto 0); result(0)<=c_in; result(32)<=i_a(31); end bhv_lshift_32; -------------------------------------------------------------------------------- Page 29 of 38 -------------------------------------------------------------------------------- ---- ARITHMETIC UNIT BEGINS [i_a(31-0), i_b(31-0), c_in, s(1-0), result(32-0)]-- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Arithmetic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end Arithmetic; architecture Bhv_Arithmetic of Arithmetic is component mux1_4to1 is Port ( a,b,c,d:in STD_LOGIC; s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC); end component; component Adder_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end component; signal sg:STD_LOGIC_VECTOR(31 downto 0); begin p0:mux1_4to1 Port map(i_b(0),not i_b(0),\'1\',\'0\',s,sg(0)); p1:mux1_4to1 Port map(i_b(1),not i_b(1),\'1\',\'0\',s,sg(1)); p2:mux1_4to1 Port map(i_b(2),not i_b(2),\'1\',\'0\',s,sg(2)); p3:mux1_4to1 Port map(i_b(3),not i_b(3),\'1\',\'0\',s,sg(3)); p4:mux1_4to1 Port map(i_b(4),not i_b(4),\'1\',\'0\',s,sg(4)); p5:mux1_4to1 Port map(i_b(5),not i_b(5),\'1\',\'0\',s,sg(5)); p6:mux1_4to1 Port map(i_b(6),not i_b(6),\'1\',\'0\',s,sg(6)); p7:mux1_4to1 Port map(i_b(7),not i_b(7),\'1\',\'0\',s,sg(7)); p8:mux1_4to1 Port map(i_b(8),not i_b(8),\'1\',\'0\',s,sg(8)); p9:mux1_4to1 Page 30 of 38 Port map(i_b(9),not i_b(9),\'1\',\'0\',s,sg(9)); p10:mux1_4to1 Port map(i_b(10),not i_b(10),\'1\',\'0\',s,sg(10)); p11:mux1_4to1 Port map(i_b(11),not i_b(11),\'1\',\'0\',s,sg(11)); p12:mux1_4to1 Port map(i_b(12),not i_b(12),\'1\',\'0\',s,sg(12)); p13:mux1_4to1 Port map(i_b(13),not i_b(13),\'1\',\'0\',s,sg(13)); p14:mux1_4to1 Port map(i_b(14),not i_b(14),\'1\',\'0\',s,sg(14)); p15:mux1_4to1 Port map(i_b(15),not i_b(15),\'1\',\'0\',s,sg(15)); p16:mux1_4to1 Port map(i_b(16),not i_b(16),\'1\',\'0\',s,sg(16)); p17:mux1_4to1 Port map(i_b(17),not i_b(17),\'1\',\'0\',s,sg(17)); p18:mux1_4to1 Port map(i_b(18),not i_b(18),\'1\',\'0\',s,sg(18)); p19:mux1_4to1 Port map(i_b(19),not i_b(19),\'1\',\'0\',s,sg(19)); p20:mux1_4to1 Port map(i_b(20),not i_b(20),\'1\',\'0\',s,sg(20)); p21:mux1_4to1 Port map(i_b(21),not i_b(21),\'1\',\'0\',s,sg(21)); p22:mux1_4to1 Port map(i_b(22),not i_b(22),\'1\',\'0\',s,sg(22)); p23:mux1_4to1 Port map(i_b(23),not i_b(23),\'1\',\'0\',s,sg(23)); p24:mux1_4to1 Port map(i_b(24),not i_b(24),\'1\',\'0\',s,sg(24)); p25:mux1_4to1 Port map(i_b(25),not i_b(25),\'1\',\'0\',s,sg(25)); p26:mux1_4to1 Port map(i_b(26),not i_b(26),\'1\',\'0\',s,sg(26)); p27:mux1_4to1 Port map(i_b(27),not i_b(27),\'1\',\'0\',s,sg(27)); p28:mux1_4to1 Port map(i_b(28),not i_b(28),\'1\',\'0\',s,sg(28)); p29:mux1_4to1 Port map(i_b(29),not i_b(29),\'1\',\'0\',s,sg(29)); p30:mux1_4to1 Port map(i_b(30),not i_b(30),\'1\',\'0\',s,sg(30)); p31:mux1_4to1 Port map(i_b(31),not i_b(31),\'1\',\'0\',s,sg(31)); p32:Adder_32bit Port map(i_a,sg,c_in,result); end Bhv_Arithmetic; ------------------------------ ARITHMETIC UNIT ENDS ---------------------------- -------------------------------------------------------------------------------- Page 31 of 38 ---------- LOGIC UNIT BEGINS [i_a(31-0), i_b(31-0), s(1-0), result(32-0)]------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Logic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end Logic; architecture Bhv_logic of Logic is component AND_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component OR_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component XOR_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component NOT_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component mux33_4to1 is Port ( a,b,c,d:in STD_LOGIC_VECTOR(32 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(32 downto 0)); end component; signal sg_and: STD_LOGIC_VECTOR(32 downto 0); signal sg_or: STD_LOGIC_VECTOR(32 downto 0); signal sg_xor: STD_LOGIC_VECTOR(32 downto 0); signal sg_not: STD_LOGIC_VECTOR(32 downto 0); begin p0:AND_32bit Port map(i_a,i_b,sg_and); Page 32 of 38 p1:OR_32bit Port map(i_a,i_b,sg_or); p2:XOR_32bit Port map(i_a,i_b,sg_xor); p3:NOT_32bit Port map(i_a,sg_not); p4:mux33_4to1 Port map(sg_and,sg_or,sg_xor,sg_not,s,result); end Bhv_logic; --------------------------------- LOGIC UNIT ENDS ------------------------------ -------------------------------------------------------------------------------- ------------- SHIFT UNIT BEGINS [i_a(31-0), c_in, s(1-0), result(32-0)]--------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Shift is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end Shift; architecture Bhv_shift of Shift is component R_Shift_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component L_Shift_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component mux33_2to1 is Port ( a:in STD_LOGIC_VECTOR (32 downto 0); b:in STD_LOGIC_VECTOR (32 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR (32 downto 0)); end component; signal sg_rshift: STD_LOGIC_VECTOR (32 downto 0); signal sg_lshift: STD_LOGIC_VECTOR (32 downto 0); begin Page 33 of 38 p0:R_Shift_32bit Port map(i_a,c_in,sg_rshift); p1:L_Shift_32bit Port map(i_a,c_in,sg_lshift); p2:mux33_2to1 Port map(sg_rshift,sg_lshift,s,result); end Bhv_shift; --------------------------------- SHIFT UNIT ENDS ------------------------------ -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- ------------------------------------ 32 BIT ALU -------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC_VECTOR (3 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end ALU_32bit; architecture Bhv_alu_32bit of ALU_32bit is component Arithmetic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component Logic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component Shift is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component mux33_4to1 is Page 34 of 38 Port ( a,b,c,d:in STD_LOGIC_VECTOR(32 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(32 downto 0)); end component; signal sg_arith :STD_LOGIC_VECTOR(32 downto 0); signal sg_logic :STD_LOGIC_VECTOR(32 downto 0); signal sg_shift :STD_LOGIC_VECTOR(32 downto 0); begin p0:Arithmetic Port map(i_a,i_b,c_in,s(1 downto 0),sg_arith); p1:Logic Port map(i_a,i_b,s(1 downto 0),sg_logic); p2:Shift Port map(i_a,c_in,s(1),sg_shift); p3:mux33_4to1 Port map(sg_arith,sg_logic,sg_shift,\"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ\",s(3 downto 2),result); end Bhv_alu_32bit; -------------------------------- 32 BIT ALU ENDS -------------------------------