VHDL coding PLZ PLZ HELP use your state machine altera boar

VHDL coding . PLZ PLZ HELP

use your state machine (altera board) to act as a password detector. You will enter a 4-character password in SW3-0. Each hex character is represented by 4 bits. you will need to implement registers that can store the password four bits at a time, one character on each clock cycle. Your registers will need to have an enable signal so that the password can only be entered in the first four clock cycles. After the 4 characters have been entered in SW3-0, disable these registers. Connect HEX3-0 to display the 4-character password entered on SW3-0 using your hex decoder . SW7-4 will serve as the password inputs. Each clock cycle, enter one 4-bit input on SW7-4. If the four password inputs match the four password characters set in SW3-0, then the green LEDs should light up. If the four password inputs do not match, then the red LEDs17-10 will light up. Once again, use KEY0 as the clock input. Use SW17 as the enable signal for your registers. When the correct password has been entered, display the password on HEX7-4.

Solution

Vhdl code for password detector library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity passwd is port ( clk : in std_logic; rst_n : in std_logic; data : in std_logic_vector(7 downto 0); start : in std_logic; pass_wd : out std_logic_vector(7 downto 0)); end passwd; architecture behave of passwd is signal pass_word : std_logic_vector(7 downto 0) := to_stdlogicvector(x\"AB\"); signal pass_cnt : std_logic_vector(7 downto 0); signal start_d : std_logic; begin -- behave process (clk, rst_n) begin -- process if rst_n = \'0\' then -- asynchronous reset (active low) start_d <= \'0\'; pass_cnt <= (others => \'0\'); elsif clk\'event and clk = \'1\' then -- rising clock edge start_d <= start; if (start_d = \'0\' and start = \'1\') then pass_cnt <= data; elsif (pass_cnt != passwd or pass_cnt != (others=> \'1\')) then pass_cnt <= pass_cnt + 1; end if; end if; end process; end behave;