Consider a byteaddressable RAM for which memory addresses ar

Consider a byte-addressable RAM for which memory addresses are 24 bits long. What is the capacity of RAM? In other words, what is the maximum number of bytes addressable? Express the result in Megabytes. Suppose this RAM is divided into small blocks, each of size 16 bytes. How many memory blocks are possible? Given a 24-bit address of a byte, we need to know which block the byte falls into and what the byte offset of the address is within the block. Draw a figure to show how the 24-bits address can be split into two parts that will help us identify the block number and the byte offset within the block. Indicate clearly the number of bits for each part. Given a 24-bit address 40AA18 (written in hexadecimal), split the address and express which block the address falls into and what the byte offset is within that block. Express the block number and byte offset in decimal.

Solution

In computer architecture, 24-bit integers, memory addresses, or other data units are those that are at most 24 bits (3 octets) wide. Also, 24-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

Notable 24-bit machines include the SDS 930 and SDS 940, the ICT 1900 series, and the Datacraft minicomputers/Harris H series.^[1]

The IBM System/360, announced in 1964, was a popular computer system with 24-bit addressing and 32-bit general registers and arithmetic. The early 1980s saw the first popular personal computers, including the IBM PC/AT with an Intel 80286 processor using 24-bit addressing and 16-bit general registers and arithmetic, and the Apple Macintosh 128K with a Motorola 68000 processor featuring 24-bit addressing and 32-bit registers.

The eZ80 is a microprocessor and microcontroller family, with 24-bit registers and therefore 24-bit linear addressing, that is binary compatible with the 8/16-bit Z80.^{[citation needed]}

The 65816 is a microprocessor and microcontroller family with 16-bit registers and 24-bit bank switched addressing. It is binary compatible with the 8-bit 6502.^[2]

The range of unsigned integers that can be represented in 24 bits is 0 to 16,777,215 (FFFFFF16 in hexadecimal). The range of signed integers that can be represented in 24 bits is 8,388,608 to 8,388,607.

Several fixed-point digital signal processors have a 24-bit data bus, selected as the basic word length because it gave the system a reasonable precision for the processing audio (sound). In particular, the Motorola 56000 series has three parallel 24-bit data buses, one connected to each memory space: program memory, data memory X, and data memory Y.^[3]

Engineering Research Associates (later merged into UNIVAC) designed a series of 24-bit drum memory machines including the Atlas, its commercial version the UNIVAC 1101, the ATHENA computer, the UNIVAC 1824 guidance computer, etc. Those designers selected a 24-bit word length because the Earth is roughly 40 million feet in diameter, and an intercontinental ballistic missile guidance computer needs to do the Earth-centered inertial navigation calculations to an accuracy of a few feet.^[4]

At any rate, with 24-bit addresses, we\'d have 224=16777216=16M224=16777216=16M possible addresses, hence that many possible chunks. If each chunk was a byte that would mean that the total addressable memory would be 16777216 bytes, or 16MB. Similarly, if each chunk was 4 bytes long, the total addressable memory would be (chunk size ×× number of addresses), or 4B×16M=64MB4B×16M=64MB.

Most modern processors do not address memory at the granularity of single bits but limit the size of the smallest chunk of memory that can be accessed to an 8-bit byte. This is called byte-addressable memory.

With byte-addressable memory, a 24-bit immediate could directly address any of 2²⁴bytes, i.e., 16 MiB.

Stallings is assuming byte-addressing, so 2²⁴bytes would be directly addressable.

In the past, some processors used word-addressable memory, where the smallest chunk that could be accessed was equal to the size of the registers. By using a larger smallest chunk size, fewer bits were needed to address a given size of memory. E.g., with a 32-bit word size, a 24-bit immediate would be able to reference 2²⁴*4 bytes (64 MiB). (Using word-addressable memory also simplified memory access.)

Outside of some DSPs and embedded systems processors, word-addressable memory is not very popular today.

As a side note, some microcontrollers have special mechanisms for atomic bit addressing such bit-band regions (e.g., ARM), where a section of the address space is bit-addressable, and atomic set and atomic clear bit instructions (e.g., MIPS), where three bits of the instruction specify the bit within a byte.)

It might also be noted that some ISAs shift immediate values by the access size (e.g., accessing a 2-byte value would shift the immediate by one bit). This assumes that the base pointer and the address of the value are properly aligned, i.e., that the least bit is zero for a 2-byte value, the two least significant bits are zero for a 4-byte value, etc. This allows a smaller immediate to provide a larger access range when accessing values larger than a byte.