Instructions are to be fetched from a dynamic ram DRAM consi

Instructions are to be fetched from a dynamic ram (DRAM) consisting of a single memory module that has a cycle time of 25 ns. Each memory access (i.e., read or write) requires 20 ns. The memory returns each 32-bit instruction over the 32-bit CPU-to-memory instruction bus. The system also contains a separate data memory consisting of a single module of DRAM that has the same cycle time as the instruction memory and transfers data over a separate 32-bit data bus. That is, the system has a Harvard Architecture. For the questions below, recall that each pipeline stage consumes 1 clock cycle. Also assume that for a) through d) below, the decode, execute and write-back pipeline stages each takes 10ns to complete.

If the instruction memory is implemented as a single memory module with a storage capacity of 256 * 2²⁰ bytes, what would be its width and depth?

Solution

256*220

width=2^8=256

8 megabits is the width

On the other hand depth is   6 or 7 depending on the parity we will take 2^7=128 as the enarest to 200.

So width =8 megabits

depth =7 megabits for DRAM