With Dlatches we can build registers which are simply blocks

With D-latches, we can build registers, which are simply blocks of latches with data inputs, clock and data lines, and data output control with tri-state buffers. Figure 4 shows a typical arrangement of D-latches as a register. Explain the correct sequence of signals needed to store the byte 0 times 37 in this register. What is the correct sequence of signals needed to write the contents of the register onto the data bus?

Solution

Tri state buffer works just like a switch when ever clock is enable (1) that data at input be the output if clock is disable(0) Just it goes to OFF state.

so 0x37 is 55 in decimal and 11101100 in binary.

If clock signal is high for first three D latches and low for one latche again high for 2 latches finally low for 2 other latches the same data at input will be the output.