A finite state machine has one input x and one output z The

A finite state machine has one input x and one output z. The state transition diagram is shown below. The VHDL code given below describes part of the FSM architecture. By writing directly in the code, complete the architecture of this FSM with asynchronous reset. library ieee; use ieee.std_logic_1164 all; casity example is port(cllc, reset: in std_logic; x: in std_logic; x: ext std_logic); end entity example; Architecture state_machine of example is Type stateType is (s0, s1, s2); signal present_state, next_state; stateType; Begin Proc: process(present_state.x) Begin Case present_state is When s0 = > If(x-\'1\') then Next_state

Solution

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fsm1 IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := \'0\';
x : IN STD_LOGIC := \'0\';
z : OUT STD_LOGIC
);
END fsm1;

ARCHITECTURE BEHAVIOR OF fsm1 IS
TYPE type_present_state IS (s0,s1,s2);
SIGNAL present_state : stateType;
SIGNAL Next_state : stateType;
BEGIN
PROCESS (clk,reset,present_state)
BEGIN
IF (reset=\'1\') THEN
present_state <= s0;
ELSIF (clk=\'1\' AND clk\'event) THEN
present_state <= Next_state;
END IF;
END PROCESS;

PROCESS (present_state,x)
BEGIN
z <= \'0\';
CASE present_state IS
WHEN s0 =>
IF ((x = \'1\')) THEN
Next_state <= s1;z<=\'0\'

ELSE
Next_state <= s1;z<=\'1\'
END IF;
WHEN s1 =>
IF ((x = \'1\')) THEN
Next_state <= s1;z<=\'0\'

ELSE
Next_state <= s2;z<=\'0\'
END IF;
  
WHEN s2 =>
IF ((x = \'1\')) THEN
Next_state <= s1;z<=\'1\'

ELSE
Next_state <= s2;z<=\'0\'
END IF;
WHEN OTHERS =>
z <= \'X\';
report \"Reach undefined state\";
END CASE;
END PROCESS;
END BEHAVIOR;