Verilog DE2 Board Clock module downclockclk50mhz clk1hz inp

Verilog - DE2 Board Clock

module downclock(clk_50mhz, clk_1hz);
   input clk_50mhz;
   output clk_1hz;
   reg clk_1hz;
   reg [24:0] count;
always @ (posedge clk_50mhz)
   begin
       if(count == 24999999) begin
           count <= 0;
           clk_1hz <= ~clk_1hz;
   end
   else begin
       count <= count + 1;
   end
end
endmodule

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Modify the Verilog Code to bring down clock from 50MHz to 8MHz.

DE2 INTERNAL CLOCK The internal oscillator of the DE2 board is to be used to clock the design. The DE2 board includes two oscillators that produce 27 MHz and 50 MHz clock signals [1]. The board also includes an SMA connector which can be used to connect an external clock source to the board. The schematic of the clock circuitry is shown in Figure 3, and the associated pin assignments appear in Table 1. C33 BC48 EN VCC 0.1U GND OUT BC99 EN VCC 50MHZ 0.1U GND OUT J5 XT CLOCK R30 1K Fig. 3. DE2 clock circuit Table 1, Pin assignments for the clock inputs Signal name CLOCK 27 CLOCK 50 EXT CLOCK FPGA Pin No PIN D13 PIN N2 PIN P26 Description 27 MHz clock 50 MHZ clock External (SMA) clock Clocks on the DE2 board work with constant speeds. To get the lower clock speed, the original clock must be brought down, for example using a counter. The example Verilog code bringing the 50 MHz clock down to 1Hz is show below:

Solution

module fredivider(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg counter[15];

always @(posedege clk or negedge rst)
begin
if(!rst)
counter<=16\'d0;
else
if(counter==16\'d5000)
counter<=16\'d0;
else
counter<=counter+1;
end

assign out_clk<=counter[15;

end module