Gate to channel capacitance 4 times 104 pFum2 Metal to subst

Gate to channel capacitance 4 \\times 10^{-4} pF/um^{2}

Metal to substrate capacitance 0.3 \\times 10^{-4} pF/um^{2}

A signal comes fom an inverter with 1.5m minimum size. Design a non-inverting output pad driver that is driven by a metal bonding pad of size 135X135 m^{2} and an external capacitive load of 1.5 pf. use min delay, equal rise and fall times.

How many stages of inverters should be used, and what would be their ratio of their successive sizes, and what is each inverter\'s size?

Solution

Table:

Best number of stages to use for various path efforts. For example, for path efforts between 3920 and 14200, seven stages should be used; the stage effort will lie in the range 3.3–3.9 delay units. The table assumes pinv = 1.0.
Path effort F   Best number of stages, Nˆ Minimum delay Dˆ Stage effort, f , range

0 1.0

1 0–5.8

5.83 6.8

2 2.4–4.7

22.3 11.4

3 2.8–4.4

82.2 16.0

4 3.0–4.2

300 20.7

5 3.1–4.1

1090 25.3

6 3.2–4.0

3920 29.8

7 3.3–3.9

14200 34.4

8 3.3–3.9

51000 39.0

9 3.3–3.9

184000 43.6

10 3.4–3.8

661000 48.2

11 3.4–3.8

2380000 52.8

12 3.4–3.8

8560000 57.4

numbers of stages of logic, it is necessary to evaluate the delay equations to determine which design is best.

electrical effort is 4/0.3 = 13.33. Table 1.3 specifies a two-stage design.

The stage effort will be ˆ f = (13.33)^1/2 = 3.65. Thus the input capacitance of each inverter in the string will be 3.65 times that of its predecessor.

The path delay will be Dˆ = 2 × 3.65 + 2 × pinv = 9.3 delay units.

This corresponds to an absolute delay of 9.3 = 0.465 ns, assuming = 50 ps.

This example finds the best ratio of the sizes of succeeding stages to be 3.65.