This is a harware thread for a very simplistic computuationa

This is a harware thread for a very simplistic computuational machine. Use your rtl knowledge to code this in SystemVerilog(or VHDL). Include a reset input that starts the FSM in the fetch state, but also ensures the first memory address accessed will be 0. Use a 16 bit memory contents. Use $monitor to show value of register A.

Your code header is this:

Draw more of the FSM re re wememory clk we data addr b1 fetch D [15:0] IdIR en register: IR clk add Q [7:0] decode ldC en a s register: CTR clk add/sub a-s = 1 ldA ldA en register: A clk Assume a s1 means add 0 means subtract

Solution

module simp_comp( clk,rst,we,re,IdA,IdC,IdIR,a_s, addr,data );

input clk,rst,we,re,IdA,IdC,IdIR,a_s;

input [15:0]addr;

output reg [15:0]data;

reg [15:0] m[6:0];

reg [7:0]IdA_reg;

reg [8:0] reg_a,IRQ;

//address logic

always@(posedge clk);

begin

if(IdC)

addr <= addr +1;

end

//memory logic

always@(posedge clk, posedge rst)

if(rst)

begin

data <= 0;

addr <= 0;

end

else

begin

if(we)

m[addr] <= data;

else if (re)

data <= m[addr];

end

//decode logic

always@(posedge clk)

if(IdIR)

IRQ <= data[15:8];

if(a_s == 1 && IdA == 1)

begin

reg_a <= IRQ + IdA_reg;

else if(a_s == 1 && IdA == 0)

reg_a <= IRQ - IdA_reg;

end

endmodule