Convert the VHDL to Verilog entity dp is port clkdp in stdlo

Convert the VHDL to Verilog

entity dp is

port (clk_dp: in std_logic;

rst_dp: in std_logic;

muxsel_dp: in std_logic_vector(1 downto 0);

imm_dp: in std_logic_vector(7 downto 0);

input_dp: in std_logic_vector(7 downto 0);

accwr_dp: in std_logic;

rfaddr_dp: in std_logic_vector(2 downto 0);

rfwr_dp: in std_logic;

alusel_dp: in std_logic_vector(2 downto 0);

shiftsel_dp: in std_logic_vector(1 downto 0);

outen_dp: in std_logic;

zero_dp: out std_logic;

positive_dp: out std_logic;

output_dp: out std_logic_vector(7 downto 0));

end dp;

architecture struct of dp is

component mux4 is

port (sel_mux: in std_logic_vector(1 downto 0);

in3_mux,in2_mux,in1_mux,in0_mux: in std_logic_vector(7 downto 0);

out_mux: out std_logic_vector(7 downto 0));

end component;

component acc is

port (clk_acc: in std_logic;

rst_acc: in std_logic;

wr_acc: in std_logic;

input_acc: in std_logic_vector (7 downto 0);

output_acc: out std_logic_vector (7 downto 0));

end component;

component reg_file is

port (clk_rf: in std_logic;

wr_rf: in std_logic;

addr_rf: in std_logic_vector(2 downto 0);

input_rf: in std_logic_vector(7 downto 0);

output_rf: out std_logic_vector(7 downto 0));

end component;

component alu is

port (sel_alu: in std_logic_vector(2 downto 0);

inA_alu: in std_logic_vector(7 downto 0);

inB_alu: in std_logic_vector(7 downto 0);

OUT_alu: out std_logic_vector (7 downto 0));

end component;

component shifter is

port (sel_shift: in std_logic_vector(1 downto 0);

input_shift: in std_logic_vector(7 downto 0);

output_shift: out std_logic_vector(7 downto 0));

end component;

component tristatebuffer is

port (E: in std_logic;

D: in std_logic_vector(7 downto 0);

Y: out std_logic_vector(7 downto 0));

end component;

signal C_aluout,C_accout,C_rfout,C_muxout,C_shiftout: std_logic_vector(7 downto 0);

signal C_outen: std_logic;

begin

U0: mux4 port map(muxsel_dp,imm_dp,input_dp,C_rfout,C_shiftout,C_muxout);

U1: acc port map(clk_dp,rst_dp,accwr_dp,C_muxout,C_accout);

U2: reg_file port map(clk_dp,rfwr_dp,rfaddr_dp,C_accout,C_rfout);

U3: alu port map(alusel_dp,C_accout,C_rfout,C_aluout);

U4: shifter port map(shiftsel_dp,C_aluout,C_shiftout);

C_outen <= outen_dp or rst_dp;

U5: tristatebuffer port map(C_outen,C_accout,output_dp); --output_dp <= C_accout;

zero_dp <= \'1\' when (C_muxout = \"00000000\") else \'0\';

positive_dp <= not C_muxout(7); --positive_dp <= \'1\' WHEN (C_muxout(7) = \'0\') ELSE \'0\';

end struct;

Convert the VHDL code to Verilog

Solution

here you are having a long code you can decrease this code.

module dp is (clk_dp,rst_dp,muxsel_dp,imm_dp,input_dp,accwr_dp,rfaddr_dp2,rfwr_dp

,alusel_dp,shiftsel_dp,outen_dp,zero_dp,positive_dp,output_dp);

//--------------mux4 Ports-----------------------

Input sel_mux (1 downto 0);

Input in3_mux;

Input in2_mux;

Input in1_mux;

Input in0_mux; (7 downto 0);

Output out_mux (7 downto 0);

//-------------acc Ports-----------------------

Input clk_acc;

Input rst_acc;

Input wr_acc;

input_acc (7 downto 0);

output output_acc (7 downto 0);

//-------------reg Ports-----------------------

Input clk_rf;

Input wr_rf;

Input addr_rf (2 downto 0);

Input input_rf (7 downto 0);

Output output_rf (7 downto 0));

  //-------------reg Ports-----------------------

Input sel_alu (2 downto 0);

Input inA_alu (7 downto 0);

Input inB_alu(7 downto 0);

Output OUT_alu (7 downto 0));

  //-------------reg Ports-----------------------

Input sel_shift(1 downto 0);

Input input_shift(7 downto 0);

Output output_shift(7 downto 0));

  //------------tristatebuffer Ports-----------------------

Input E;

Input D(7 downto 0);

Output Y(7 downto 0));

Output signal C_aluout;

Output C_accout;

Output C_rfout;

Output C_muxout,

Output C_shiftout (7 downto 0);

Reg signal C_outen;

begin

U0: mux4 port map(muxsel_dp,imm_dp,input_dp,C_rfout,C_shiftout,C_muxout);

U1: acc port map(clk_dp,rst_dp,accwr_dp,C_muxout,C_accout);

U2: reg_file port map(clk_dp,rfwr_dp,rfaddr_dp,C_accout,C_rfout);

U3: alu port map(alusel_dp,C_accout,C_rfout,C_aluout);

U4: shifter port map(shiftsel_dp,C_aluout,C_shiftout);

C_outen <= outen_dp or rst_dp;

U5: tristatebuffer port map(C_outen,C_accout,output_dp); --output_dp <= C_accout;

zero_dp <= \'1\' when (C_muxout = \"00000000\") else \'0\';

positive_dp <= not C_muxout(7); --positive_dp <= \'1\' WHEN (C_muxout(7) = \'0\') ELSE \'0\';

end module;