A TTL gate has the following actual voltage values VIHmin 2

A TTL gate has the following actual voltage values: VIH(min) = 2.25V, VIL(max)=0.65V. Assuming it is being driven by a gate with VOH(min) = 2.4V and VOL(max) = 0.4V, calculate the HIGH and LOW level noise margins. Calculate the maximum amplitude of noise spikes that can be tolerated on the inputs in the HIGH state and LOW state for this gate.

Solution

Logic Gates are designed to operate only at two states 1. High(1) and 2. Low(0).

It will take its input and produce its output as 1. High(1) and 2. Low(0).

But high and low are interpreted by a Gate by some level of voltage. and this level may be different for different Gates fabricated by different logic family technology.

There is no wonder if high state voltage are different for driver and driven Gates.

High noise margin is given by difference of high state voltage of driver Gate and that of driven Gate. i.e.

NM_OH = Voh - Vih = 2.4 V - 2.25 V = 0.15 V

and Low noise margin is given by difference of low state voltage of driven Gate and that of driver Gate. i.e.

NM_OL = ViL - VoL = 0.65 V - 0.4 V = 0.25V

Input in the range of 2.25 V to 2.40 V will be read as High state and in the range of 0.4 V to 0.65 V will be read as low state. The Gate can withstand with Noise amount to the calculated noise margin without changing its state.

the noise spike\'s maximum amplitude which can be tolerated at input for high state is: - 0.15 V .

and the noise spike\'s maximum amplitude which can be tolerated at input for low state is: 0.25 V.