For the circuit below calculate the minimum period of the cl

For the circuit below, calculate the minimum period of the clock signal, T_min, and determine whether any hold time violations occur in the circuit.

Solution

Tmin = tcQ + tNOT + tsu

Since we are interested in the longest delay for this calculation, the maximum value of tcQ should be used.

For the calculation of tNOT we will assume that the delay through any logic gate can be calculated as 1 + 0.1k, here k is the number of inputs to the gate. For a NOT gate this gives 1.1 ns, which leads to

Tmin = 1.0 + 1.1 + 0.6 = 2.7 ns
Fmax = 1/2.7 ns = 370.37 MHz

the shortest possible delay from a positive clock edge to a change in the value of the D input. The delay is given by tcQ + tNOT = 0.8 + 1.1 = 1.9 ns. Since 1.9 ns > th = 0.4 ns there is no hold time violation.