Hi I am trying to design a 4bit wide 4register file which wo

Hi, I am trying to design a 4-bit wide 4-register file which works by writing and reading from the register file and uses 7-seg LED to show the contents of the register file. However as you can see in the picture there are some errors in implementing it. Could someone point out what am I doing wriong and explain how I need to correct this error. I am really confused. The first block is a 2-to-1 decoder connected to the register file whichis further connected to the seven seg display. Please explain what am I doing wrong!!

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Solution

4-Bit Shift Register library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Shift_register_VHDL is port( clk: in std_logic; L,w: in std_logic; Output: out std_logic_vector(3 downto 0); Input: in std_logic_vector( 3 downto 0)); end Shift_register_VHDL; architecture Behavioral of Shift_register_VHDL is begin process variable temp: std_logic_vector(3 downto 0); begin wait until rising_edge (clk); temp := Input; if L=\'1\' then for i in 0 to 2 loop temp(i) := temp(i+1); end loop; temp(3) := w; --what does this line mean? for shift and load a new value / Looks weird to me. end if; Output <= temp; end process; end Behavioral;