Answer the questions that follow the VHDL code given below L

Answer the questions that follow the VHDL code given below. LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex1_IS PORT (n, cp, n rd: IN st_logic; q: BUFFER integer RANGE 0 TO 15); END ex1; ARCHITECTURE are OF ex1 IS BEGIN PROCESS (n_cp, n_rd) BEGIN IF (n_rd = \'0\') THEN q

Solution

a)n_rd- used to reset the counter

n_cp-used as clock to the counter

b)4 binary bits are there in q;

Q stores 0 t0 15 number so

log2(16)=4