This Task Must be Done using Quartez II software and modelsi

This Task Must be Done using Quartez II software and modelsim , with results explanantion .

Shows a 4-to-l multiplexer with 4-bit input each and 4-bit output. Represent the multiplexer using:- (i) Schematic design entry technique with gate level representation. (ii) HDL-based design technique a. if-else: b. case statement; c. Demonstrate the effect of complete and incomplete case (a) and case (iii) Differentiate between the schematic and HDL-based design technique and relate to abstraction levels in digital design.

Solution

mux using if staement:

module muxif( select, A,B,C,D,Y );

input[1:0] select;
input A,B,C,D;
output Y;

reg Y;
wire[1:0] select;
wire A,B,C,D;

always @( select )
begin
if( select == 0)
Y = A;

if( select == 1)
Y = B;

if( select == 2)
Y= C;

if( select == 3)
Y = D;
end

endmodule

Mux using case statemnt:

module muxcase( select,A,B,C,D,Y );

input[1:0] select;
input A,B,C,D;
output Y;

reg Y;
wire[1:0] select;
wire A,B,C,D;

always @( select )
begin
case( select )
0 : Y = A;
1 : Y = B;
2 : Y = C;
3 : Y = D;
endcase
end

endmodule;

Mux using Structural or schematic:

module muxsch( select, A,B,C,D,Y);

input[1:0] select;
input A,B,C,D;
output Y;

wire Y, q1, q2, q3, q4, NOTselect0, NOTselect1;
wire[1:0] select;
wire A,B,C,D;

not n1( NOTselect0, select[0] );
not n2( NOTselect1, select[1] );

and a1( q1, NOTselect0, NOTselect1, A );
and a2( q2, select[0], NOTselect1, B );
and a3( q3, NOTselect0, select[1], C );
and a4( q4, select[0], select[1], D );

or o1( Y, q1, q2, q3, q4 );

endmodule