Question 1 Consider the following sequence of control signal

Question 1

Consider the following sequence of control signals for the simple processor architecture shown in Figure 1. 1. Enable A in, Rx out 2. Enable G in, Ry out, Add/Sub = 0 3. Enable Rx in, G out, Done The instruction being implemented by this sequence is:

a) ADD Rx, Ry

b) SUB Rx, Ry

c) LOAD Rx, Data

d) MOV Rx, Ry

Question 2

Consider the following sequence of control signals for the simple processor architecture shown in Figure 1. 1. Enable Rx in, Extern, Done The instruction being implemented by this sequence is:

a) ADD Rx, Ry

b) SUB Rx, Ry

c) LOAD Rx, Data

d) MOV Rx, Ry

Question 3

Consider the following sequence of control signals for the simple processor architecture shown in Figure 1. 1. Enable Rx in, Ry out, Done The instruction being implemented by this sequence is:

a) ADD Rx, Ry

b) SUB Rx, Ry

c) LOAD Rx, Data

d) MOV Rx, Ry

Question 4

Consider the following sequence of control signals for the simple processor architecture shown in Figure 1. 1. Enable A in, Rx out 2. Enable G in, Ry out, Add/Sub = 1 3. Enable Rx in, G out, Done The instruction being implemented by this sequence is:

a) ADD Rx, Ry

b) SUB Rx, Ry

c) LOAD Rx, Data

d) MOV Rx, Ry Qu

Data Bus Clock RO R3 RO Ro our eaf Extern Control circuit Function Don

Solution

question 1

option a) is correct

question 2

option c is correct

question 3

option d is correct

question 4

option b is correct