Show me how to implement a boolean equation in verilog using
Show me how to implement a boolean equation in verilog using only non-blocking statements. F = (A + B).C’
Solution
Solution:Verilog, circuit components are designed inside a module. Modules can contain both structural and behavioral statements. Structural statements represent circuit components like logic gates, counters, and microprocessors. Behavioral level statements are programming statements that have no direct mapping to circuit components like loops, if-then statements, and stimulus vectors which are used to exercise a circuit.
Verilog Basics
The keyword assign is used to set the value of outputs or wires. Parentheses can be used to correctly order Boolean operators to fashion the function you are trying to express.
Here\'s an example with 3 inputs and 1 outputs, defined using Boolean operators:
assign f = c | temp; // c or temp
endmodule
| module example(a, b, c, f); |
| input a, b, c; |
| output f; |
| wire temp; |
| assign temp = ~( a & b); // a nand b |
| assign f = c | temp; // c or temp endmodule |
