1 Do you think that a specific CPU name and memory model mus

1. Do you think that a specific CPU name and memory model must be defined in an assembly program? (explain) Also, illustrate the relationship between the endian orders (big or little) and the main memory regarding the CPU-memory communication

Solution

CPU(central processing unit) which controls parts of the computer and performing various calculations and operations with data.The CPU name must be defined in assembly language.Memory model can be defined even in high level languages.

n order to understand the concept of big and little endian, you need to understand memory. Fortunately, we only need a very high level abstraction for memory. You don\'t need to know all the little details of how memory works.

All you need to know about memory is that it\'s one large array. But one large array containing what? The array contains bytes. In computer organization, people don\'t use the term \"index\" to refer to the array locations. Instead, we use the term \"address\". \"address\" and \"index\" mean the same, so if you\'re getting confused, just think of \"address\" as \"index\".

Each address stores one element of the memory \"array\". Each element is typically one byte. There are some memory configurations where each address stores something besides a byte. For example, you might store a nybble or a bit. However, those are exceedingly rare, so for now, we make the broad assumption that all memory addresses store bytes.

I will sometimes say that memory is byte-addresseable. This is just a fancy way of saying that each address stores one byte. If I say memory is nybble-addressable, that means each memory address stores one nybble.

In big endian, you store the most significant byte in the smallest address.

In little endian, you store the least significant byte in the smallest address

Notice that this is in the reverse order compared to big endian

The CPU puts the address it wants on its output address lines, often 32 to 64 bits worth. Then when the lines have settled to their new value, in a nanosecond or so, the CPU raised the \"address ready\" line, telling the memory that it\'s now a good time to read the address lines.   When that line goes up, the memory raises its \"wait\" line. A short while later, the memory has found the data and it puts the data on its data out lines, 8, 16, 32, 64, or 128 of them. A short while later it drops the \"wait\" line, which tells the CPU it\'s now a good time to read the data lines.

That\'s just a basic and simple memory cycle. There are more complex cycles, for instance if there are multiple CPUs talking to the memory, the CPU has to first request and win access to the bus.

Also in many situations the CPU needs to have exclusive access for one cycle or more, so it raises a \"HOLD\" line, telling other devices to not even think of asking for access to memory.

Also quite often a CPU will want to request a sequential block of memory, in which case it can raise a \"burst request\" line, and the memory might return 16, 32, 64, 128, or 256 items, without all the inter-request folderols.

Some of the newest memories just assume the CPU will want blocks every time, which is reasonable, as most CPUs have a instruction and data cache which can accept blocks of data.

Also the newest and fastest memories use both edges of the strobe pulses, sending data on both the rising and the falling edges of the clock. This either doubles the data rate or allows the clock line to be less critical in its driving current and routing.