Use the Xilinx tools to define simulate and implement an 83

Use the Xilinx tools to define, simulate and implement an 8-3 priority encoder with Enable In, Enable Out, and Group Signal. Submit your source and bit files.

Solution

frist we have to define input and output terminals of encoder module here encoder is of 8-3 then input is 8 bit length and output is 3 bit length and enable is 1 bit here consder enable is of active low signal

by using truth table we will write code with the help of case statement as shown

module encoder83(
input  en,
input  [7:0]in,
output reg [2:0]out);

   always@(*)
   begin
       if(!en) //Active low enable
           out = 0;
       else begin
           case ({in})
           8\'b0000_0001 : out =3\'b000;
           8\'b0000_0010 : out =3\'b001;
           8\'b0000_0100 : out =3\'b010;
           8\'b0000_1000 : out =3\'b011;
           8\'b0001_0000 : out =3\'b100;
           8\'b0010_0000 : out =3\'b101;
           8\'b0100_0000 : out =3\'b110;
           8\'b1000_0000 : out =3\'b110;
           default      : out =3\'bxxx;
           endcase
       end
   end

endmodule



TestBench using $random and Tasks

module tb_encoder83;

    reg en;
    reg  [7:0]in;
    wire [2:0] out;
    
    encoder83 ENC (.en(en),.in(in),.out(out));    
    
    initial begin
        en =0;
        in =0;
        repeat(10)
        random_generation(in,en);
        #45 $finish;
    end
    
    task random_generation;
    output [7:0]in_t;
    output en_t;
    begin
        #4;
        in_t = $random % 8;
        en_t =$random;
    end
    endtask
    
    
    task display;
    input en_t;
    input [7:0]in_t;
    input [2:0]out_t;
        $display(\"time =%0t \\t INPUT VALUES \\t en =%b in =%b \\t OUTPUT VALUES out =%b\",$time,en_t,in_t,out_t);
    endtask
    
    always@(out)
       display(en,in,out);

endmodule

output

time =0          INPUT VALUES    en =0 in =00000000      OUTPUT VALUES out =000
time =4          INPUT VALUES    en =1 in =00000100      OUTPUT VALUES out =010
time =8          INPUT VALUES    en =1 in =11111001      OUTPUT VALUES out =xxx
time =16         INPUT VALUES    en =0 in =11111101      OUTPUT VALUES out =000
time =24         INPUT VALUES    en =1 in =00000110      OUTPUT VALUES out =xxx
time =28         INPUT VALUES    en =0 in =00000101      OUTPUT VALUES out =000
time =40         INPUT VALUES    en =1 in =00000101      OUTPUT VALUES out =xxx

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit

demo board.

To create a new project:

1. Select File > New Project... The New Project Wizard appears.

2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial

subdirectory is created automatically.

4. Verify that HDL is selected from the Top-Level Source Type list.

5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:

Product Category: All

Family: Spartan3

Device: XC3S200

Package: FT256

Speed Grade: -4

Top-Level Source Type: HDL

Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISE Simulator (VHDL/Verilog)

Preferred Language: Verilog (or VHDL)

Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields.

When the table is complete, your project properties will look like the following:

Create the top-level Verilog source file for the project as follows:

1. Click New Source in the New Project dialog box.

2. Select Verilog Module as the source type in the New Source dialog box.

3. Type in the file name counter.

4. Verify that the Add to Project checkbox is selected.

5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown

below:

7. Click Next, then Finish in the New Source Information dialog box to complete the new

source file template.

8. Click Next, then Next, then Finish.