Write a behavioral VHDL code module for a 6bit updown counte

Write a behavioral VHDL code module for a 6-bit up-down counter. If U = 1, and D = 0, the counter will count up, and if U=0, and D=1, the counter will count down. If U = D = 0, or U = D = 1, the counter will hold its state. The counter should also have an asynchronous active-low preset signal PreN that sets all flip-flips to 1. Please type or write neatly. Test and provide code for these test cases. - preset - set U = 0 0 0 1 1 1 - set D = 1 1 1 0 0 0

Solution

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity up_dn_counter_top is Port ( CLK : in STD_LOGIC; -- input clock -- LEDs to display count LED : out STD_LOGIC_VECTOR (7 downto 0); DIR : in STD_LOGIC); -- direction of counter (up or down) end up_dn_counter_top; architecture Behavioral of up_dn_counter_top is signal clk_div : STD_LOGIC_VECTOR (3 downto 0) := X\"0\"; signal count : STD_LOGIC_VECTOR (7 downto 0) := X\"00\"; begin -- clock divider process (CLK) begin if (CLK\'Event and CLK = \'1\') then clk_div <= clk_div + \'1\'; end if; end process; -- up/down counter process (clk_div(3), DIR) begin if (clk_div(3)\'Event and clk_div(3) = \'1\') then if (DIR = \'1\') then count <= count + \'1\'; -- counting up elsif (DIR = \'0\') then count <= count - \'1\'; -- counting down end if; end if; end process; -- display count on LEDs LED <= not count; end Behavioral;