Microprocessors 2 Suppose you have a perfect clock signal wi

Microprocessors

2. Suppose you have a perfect clock signal with a frequency of 50 MHz.write the architectural body of a VHDL code that generates the following two clocks with only using one counter (20 points) T1 2.56 us CLK1 CLK2 12 st us or us. architecture Behavioral of mid2016Q2 is

Solution

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS

COMPONENT test
PORT(clk : IN std_logic;)
END COMPONENT;

signal clk : std_logic := \'0\';
constant clk_periodon : time := 320 ns;
constant clk_periodoff : time := 40960 ns;

BEGIN

uut: test PORT MAP (clk => clk);   

-- Clock process definitions
clk_process :process
begin
clk <= \'0\';
wait for clk_periodoff; --for 20.48 micro seconds signal is \'0\'.
clk <= \'1\';
wait for clk_periodon; --for next 2.56 micro seconds signal is \'1\'.
end process;

END;