Write the a VHDL text file for an EXCLUSIVENOR gateUse A B a

Write the a VHDL text file for an EXCLUSIVE-NOR gate.Use A, B, as inputs and Y as the output. Use BIT signal types.

Solution

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY EX_NOR IS

port(A,B:in bit;

Y:out bit);

end entity;

architecture dataflow of ex_nor is

begin

Y<= A xnor B;

end architecture;